The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 27, 1994
Filed:
Apr. 20, 1993
Kazuhiro Ohara, Hamamatsu, JP;
Kazushi Tamai, Hamamatsu, JP;
Yamaha Corporation, Hamamatsu, JP;
Abstract
In a communication network system such as a local area network (i.e., LAN), a plurality of repeating stations each providing a data repeating apparatus are linked together by a transmission line, wherein serial data of which significant data portion is sandwiched by delimiters is transferred. This serial data is received and repeated by the data repeating apparatus, from which it is sent out to the next station. When detecting the delimiter, this apparatus produces a delimiter timing signal. On the basis of this delimiter timing signal, a first conversion timing signal synchronized with the receiving clock is generated, while a second conversion timing signal synchronized with the sending clock is also generated. The receiving serial data is temporarily converted into parallel data by the first conversion timing signal, and then, this parallel data is re-converted into serial data by the second conversion timing signal. This serial data is sent out from the repeating station. Herein, a preamble portion (i.e., invalid-bit portion) is automatically formed on the basis of the maximum number of the drop-out bits corresponding to the number of the repeating stations linked together by the transmission line, so that this preamble portion is sent out with the re-converted serial data. When a period difference between the first and second conversion timing signals exceeds the predetermined allowable value, the bit-conversion size (e.g., 8 bits or 16 bits) is changed so as to avoid the bit-overflow phenomenon.