The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 27, 1994
Filed:
Nov. 01, 1993
Applicant:
Inventors:
Jeffrey A Werner, San Jose, CA (US);
Daniel R Watkins, Los Altos, CA (US);
Jimmy S Wong, Cupertino, CA (US);
Yen C Chang, Saratoga, CA (US);
Assignee:
LSI Logic Corporation, Milpitas, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364488 ; 364578 ;
Abstract
A logic compiler wherein verification of a generated circuit model is performed automatically by comparing the operation of the circuit model with that of a corresponding mathematical behavior model. A novel user interface and circuit model generation means enables the user to obtain, in real time, performance specifications on the circuit selected by the user as well as incurring other benefits.