The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 27, 1994
Filed:
Apr. 05, 1993
C Christopher Hanke, III, Austin, TX (US);
William F Johnstone, Austin, TX (US);
Michael W Hodel, Mesa, AZ (US);
Tzu-Hui P Hu, Tempe, AZ (US);
Barry Heim, Mesa, AZ (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
A delay matching circuit has a first node (48), a second node (50), a first loading circuit (54, 56), a second loading circuit (58, 60), a third loading circuit (64) and a buffer circuit (62). The first loading circuit couples a first logic state to the first node responsive to a first state of a control signal. The second loading circuit couples a second logic state to the first node responsive to a second state of the control signal. The buffer circuit electrically couples the first and second nodes. The first loading circuit, second loading circuit and buffer circuit are characterized by a first, a second and a third predetermined electrical impedance, respectively. The third loading circuit is coupled to the second node and is characterized by a fourth predetermined electrical impedance. The disclosed delay matching circuit propagates a clock signal input with a delay equal to the Clock-to-Q delay associated with a flip-flop constructed with similar circuit elements. The disclosed delay matching circuit is useful in circuits, such as phase locked loops, where the simultaneous propagation of two signals is critical.