The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 1994

Filed:

Jun. 15, 1992
Applicant:
Inventor:

Minoru Taguchi, Oomiya, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
257574 ; 257198 ; 257592 ; 257512 ; 257555 ; 257615 ; 257616 ; 257525 ;
Abstract

A heterojunction type of compound semiconductor integrated circuit in which a PNP transistor has an N type substrate made of a first compound semiconductor for mounting the PNP transistor and for insulating positive holes transmitted in the PNP transistor, a P type second compound semiconductor limitedly arranged on a part of the substrate for functioning as an emitter of the PNP transistor, an N type third compound semiconductor arranged on both the second compound semiconductor and the substrate for functioning as a base of the PNP transistor, electrons being applied from the substrate to the third compound semiconductor, a P type fourth compound semiconductor limitedly arranged on a part of the N type third compound semiconductor, a P.sup.+ type fifth compound semiconductor arranged on the part of the fourth compound semiconductor for functioning as a collector contact layer of the PNP transistor, an emitter contact layer limitedly arranged on a second part of the second compound semiconductor for supplying positive holes to the second compound semiconductor, the surface of the emitter contact layer being the same height as that of the fifth compound semiconductor so as to form a flat surface, and an isolation region sandwiched between the emitter contact layer and the fifth compound semiconductor for electrically isolating the emitter contact layer from both the second P.sup.+ type fifth compound semiconductor and the fourth compound semiconductor.


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