The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 20, 1994

Filed:

Nov. 23, 1993
Applicant:
Inventors:

Young K Kim, Kyungki, KR;

Kyung S Kim, Seoul, KR;

Min H Park, Seoul, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 44 ; 437 40 ; 437 41 ; 437 45 ; 437 56 ; 437 57 ; 437203 ;
Abstract

A method for fabricating an LDD MOS transistor having an improved structure capable of simplifying the fabrication and improving characteristics of the transistor. The methods includes the steps of forming a field oxide film for an active region isolation on a silicon substrate, thickly depositing an oxide film and etching the thick oxide film to form a first opening over an active region, forming side wall spacers in the first opening, implanting p type impurity ions in the silicon substrate through the first opening to form a channel region, filling the first opening with a first polysilicon film, removing the spacers to form second openings respectively in both sides of the first polysilicon film, implanting n type impurity ions in the silicon substrate through the second openings to form low concentration source and drain regions respectively disposed adjacent to both lateral ends of the channel region, removing the first polysilicon film to form a third opening, growing an oxide film over the resulting structure to form a gate oxide film, filling the third opening with a second polysilicon film, patterning the gate oxide film, and implanting n type impurity ions in the silicon substrate to form high concentration source and drain regions respectively disposed adjacent to the low concentration source and drain regions.


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