The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 20, 1994

Filed:

Aug. 19, 1993
Applicant:
Inventors:

Yasuhiro Nasu, Sagamihara, JP;

Kenji Okamoto, Hiratsuka, JP;

Jun-ichi Watanabe, Kawasaki, JP;

Tetsuro Endo, Atsugi, JP;

Shinichi Soeda, Hiratsuka, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 40 ; 437108 ; 437181 ; 437236 ; 437913 ;
Abstract

A method of manufacturing an active matrix display device, in which particular emphases are laid on the forming step of an insulation layer by the ALE method and the precedent and subsequent steps thereof, thereby insulation layer being anyone among gate insulation layer, inter-busline insulation layer, protection layer and auxiliary capacitor insulation layer comprised in the display device. The method of forming the insulation layer comprises the predetermined number of repeated cycles of the steps of subjecting a substrate to the vapor of a metal inorganic/organic compound, which can react with H.sub.2 O and/or O.sub.2 and form the metal oxide, under molecular flow condition for duration of depositing almost a single atomic layer, and next subjecting the surface of thus formed metal inorganic/organic compound layer to the H.sub.2 O vapor and/or O.sub.2 gas under molecular flow condition for duration of replacing the metal inorganic/organic compound layer to the metal oxide layer. The subsequent steps after forming of the insulation layer include deposition steps of silicon nitride and amorphous silicon layers using the same plasma CVD apparatus. The molecular flow condition is obtained by maintaining the pressure in a reaction chamber within a range between 1 and several tens of milli-Torr.


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