Semiconductor memory device and method of testing the same

Abstract

Provided are a row address circuit for driving all word lines at one time so as to select all memory cells in a memory circuit when receiving a writing control signal for test and a column address circuit for writing some particular pattern of test data which corresponds to a data specifying signal into the memory cells at one time via all pairs of bit lines when receiving the writing control signal. Also, provided in the memory circuit is a test circuit for judging at one time whether the data held in each memory cell conforms with an expected value thereof. Thus a time required for testing a semiconductor memory device of a large capacity is reduced.