The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 13, 1994

Filed:

Nov. 05, 1991
Applicant:
Inventor:

Tai Shiraishi, Nara, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G / ;
U.S. Cl.
CPC ...
345-2 ; 345115 ; 345185 ;
Abstract

An image display device displays an identical image based on display data output from a display control circuit on its own display panel and an external display unit connected to the device through an interface. The device can erase and freeze an image on the external display unit in an erase mode and a freeze mode, respectively, while the display panel displays different images. In order to do so, this device has a frame memory circuit for storing and outputting display data received from the display control circuit toward the external display unit and a disable circuit for stopping data received from the frame memory circuit from being output and instead outputting monochromatic or single-color data to the external display unit. The frame memory circuit inhibits data stored in its memory from being rewritten during the freeze mode. The disable circuit outputs the monochromatic data in the erase mode. During the freeze mode and the erase mode, the display panel can display a freeze sign and an erase sign, respectively, along with an image, by means of a sign pattern generator and a synthesize circuit. The sign pattern generator, the synthesize circuit, the frame memory circuit and the disable circuit are controlled by a control circuit which is also controlled by a CPU.


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