Integrated circuit probing apparatus including a capacitor bypass

Abstract

A device for testing the performance of high speed integrated circuits (ICs) while in wafer form or separated from the wafer which includes first and second spaced-apart probes fixedly mounted on a support member for accurately positioning the first and second probes in three dimensions for contacting at least one first point and a second point, respectively, on an IC under test. The first and second probes are interconnected at a predetermined portion of their length by a capacitor means which provides sufficient flexibility so as to facilitate independent movement of the first and second probes and avoid introducing parameters (e.g., inductance) which interfere with high speed testing of the IC. In one embodiment, the first probe is a transmission line probe (e.g., a coaxial line) and the second probe is a wire probe for supplying power to the second point on the IC. In a another embodiment, the first and second probes are wire probes for providing a reference potential and power, respectively, to respective first and second points on the IC. The capacitor means can consist of just a foil type capacitor, or a capacitor in series with a flexible metal strip having dimensions to minimize inductance for electrically interconnecting the first and second probes. The capacitor functions to block direct current and pass A.C. signals when required.