The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 13, 1994
Filed:
Aug. 31, 1993
Tsuyoshi Muramatsu, Tenri, JP;
Manabu Onozaki, Nara, JP;
Sharp Kabushiki Kaisha, Osaka, JP;
Abstract
A self-timed clocking transfer control circuit includes a flipflop for storing a transition of a transfer request signal to an L level and outputting an H level signal, an inverter for applying a transfer acknowledge signal to a preceding stage, a 5-input NAND gate, and a second signal output circuit for applying a transfer request signal to a succeeding stage in response to a transition of the output of the 5-input NAND gate to the L level. The 5-input NAND gate does not output the L level unless the transfer request signal from the preceding stage, the output of the flipflop, the transfer acknowledge signal from the succeeding stage, the transfer request signal output by the self-timed clocking transfer control circuit itself, and the prohibition signal are all in the H level. Setting the prohibition signal to the L level, self-synchronous type transfer control can be prohibited. A circuit for generating such a prohibition signal based on a signal for setting an operational mode, a clock signal, and the transfer request signal from the preceding stage may additionally be provided.