The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 13, 1994

Filed:

Feb. 02, 1994
Applicant:
Inventors:

Roger L Miller, San Jose, CA (US);

Thomas P Harper, Sunnyvale, CA (US);

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
B60T / ;
U.S. Cl.
CPC ...
303 92 ; 1881 / ; 303 20 ;
Abstract

An anti-lock braking system includes three integrated circuits (an integrated voltage regulator and two different microcontrollers) which perform different functions but share the tasks of detecting malfunctions and shutting down the system when malfunctions are detected. The two different microcontrollers perform different functions, have different circuitry, and execute different software. Typically, a first microcontroller receives wheel sensor signals, calculates wheel velocities and accelerations, and operates mechanical devices which control braking. A second microcontroller executes the main anti-lock braking software and determines from the velocities and accelerations when brakes should be released. All of the integrated circuits monitor each other and the other elements of the anti-lock braking system to detect malfunctions. Multiple shut down methods are provided so that a single chip failure can be safely handled. The three integrated circuits can be fabricated using different device technologies and design rules so that the operating environment of the anti-lock braking system is less likely to cause simultaneous failures in multiple integrated circuits.


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