The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 06, 1994

Filed:

Nov. 10, 1992
Applicant:
Inventors:

Jonel George, Pleasant Valley, NY (US);

Roger E Hough, Highland, NY (US);

Moon J Kim, Wappingers Falls, NY (US);

Allen H Preston, Poughkeepsie, NY (US);

David E Stucki, Poughkeepsie, NY (US);

Charles F Webb, Poughkeepsie, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395400 ; 3642282 ; 364247 ; 3642478 ; 3642563 ; 364D / ;
Abstract

Enables a host (hypervisor) to access any location in any guest zone in a large memory, when host and guest operands have small addresses that cannot access locations outside of their own zones. System hardware/microcode provides a particular number of windows for host use. Each CPU in the system has one or more window access registers (WARs), and one or more window registers (WRs). The host uses a load WAR instruction to designate each page frame (PF) in the host zone to be used as a host window, and each PF is associated with a respective window number. When the host receives an interception signal requiring the host to access a guest location represented by a guest zone identifier and a guest small address, the host designates one of its window numbers for an access to this guest location. Then, the host executes an activate WR instruction which invokes CPU hardware/microcode that generates a large absolute address for accessing this guest location in the large memory and stores it in a WR associated with the window number. When the host thereafter executes any instruction with an operand small address accessing the host window PF associated with that WR, and CPU hardware/microcode automatically substitutes that guest large address in the WR for the host operand small address for accessing the guest location.


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