Video timing and display id generator

Abstract

An apparatus and a method of generating video timing information and display ID information wherein the video timing generator includes a memory, typically a random access memory, which stores video timing information. A control logic device couples the information from memory to a FIFO. The control device further couples the initial information from the FIFO to a second memory, typically a register, and a sequential counter. After initial loading of information in the second memory and sequential counter, the sequential counter determines when the second memory and itself will be loaded with the next set of information. Once the sequential counter reaches zero, it generates a signal enabling itself and the second memory to load the next set of information. The display ID generator includes a memory which stores display ID information. A control logic device couples the information from the memory to a first FIFO. A state machine accesses the information held in the first FIFO and determines the duration information. Next, the state machine couples the information to a second FIFO. Last, the information in the second FIFO is coupled to a third memory and a sequential counter. After initial loading of information in second memory and sequential counter, the sequential counter determines when second memory and itself will be loaded with the next set of information. Once the sequential counter reaches zero, it generates a signal enabling itself and the second memory to load the next set of information.