The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 06, 1994
Filed:
Mar. 22, 1994
James D Hagerty, Tiverton, RI (US);
The United States of America as represented by the Secretary of the Navy, Washington, DC (US);
Abstract
A circuit for amplifying an input signal comprises an operational amplifi a dual operational amplifier, and a buffering operational amplifier all cascaded in the aforementioned order. The first operational amplifier amplifies the input signal with minimum noise degradation, is set up as a non-inverting amplifier stage, and has a local negative feedback loop comprising a resistor and capacitor in parallel. The dual operational amplifier has two amplifying devices. One device forms a second amplifying stage which increases the gain of the pre-amplified input signal and has a local negative feedback loop comprising a resistor. The other device is a third operational amplifier which combines with the buffering operational amplifier to form an amplifying and buffering stage. The third operational amplifier connects in series to the output of the second amplifying stage. The buffering operational amplifier connects in series to the output of the third operational amplifier and buffers the amplified signal at this output. The amplifying and buffering stage has a two-stage feedback loop comprising a resistor connected between the output of the buffering operational amplifier and the inverting input of the third operational amplifier. A four-stage feedback loop includes a resistor and capacitor in parallel and connects between the output of the buffering operational amplifier and the inverting input of the first operational amplifier.