The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 29, 1994
Filed:
Nov. 18, 1992
Junichi Shikatani, Kawasaki, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
A semiconductor integrated circuit device includes a logic cell array having a plurality of logic cells arranged in a matrix having a plurality of rows and columns. The logic cells respectively have input terminals and output terminals. Also, the device includes interconnection lines mutually connecting the logic cells via the input and output terminals of the logic cells so that desired logic circuits are formed, and a plurality of switches which are respectively provided for the logic cells and selectively connect the output terminals of the logic cells to the interconnection lines. Further, the device includes a test circuit for directly supplying the input terminals of the logic cells with desired data used for testing the semiconductor integrated circuit device in a state where a plurality of switches selectively disconnect the output terminals of the logic cells from the interconnection lines. The output line of a cell is disconnected from the interconnection line to the input of the following cell. The interconnection line is then connected to an input/output line which is switched to an input state and the desired test signal is supplied to the input of the following cell. The state of the following cell can then be evaluated to delete errors in the cell performance.