The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 29, 1994

Filed:

Dec. 23, 1992
Applicant:
Inventor:

Teruo Kusaka, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K / ;
U.S. Cl.
CPC ...
29840 ; 29593 ;
Abstract

A method of fabricating an integrated circuit chip package is provided in which a multi-chip module is formed by mounting a plurality of IC chips on a single silicon circuit board by means of flip-chip interconnection. Compared with a conventional multi-chip module in which, in order to obtain a uniform gap between IC chips and a silicon circuit board, metal bumps provided on both the silicon circuit board and the IC chips are used, such gap is defined in the present method by thicknesses of organic insulating films formed on both the IC chips and the circuit board. That is, height of metal bumps is selected such that it is smaller than a sum of the thicknesses of the insulating films and that closed spaces due to melting of solder for metal bump connection is prevented from being formed between the organic insulating films.


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