Structure and method for programming antifuses in an integrated circuit

Abstract

This invention provides a structure and method for interconnecting logic devices through line segments which can be joined by programming antifuses. One of several programming lines can be connected through an interconnect line segment to each terminal of each antifuse in the array. Interconnect line segments connected to opposite terminals of the same antifuse are connected to a different programming line in order to be able to apply different voltages to the two terminals of the antifuse. An addressing structure selectively connects interconnect line segments to their respective programming lines, and programming voltages applied to the programming lines cause a selected antifuse to be programmed. A novel addressing feature sequentially addresses two transistors for the line segments to be connected, and takes advantage of a capacitive pumped decoder to maintain the addressed transistors turned on while programming voltages are applied. The structure also allows for testing of logic devices by applying test voltages to the programming voltage lines and/or sensing logic device output on programming voltage lines. The structure and method also permit measuring resistance of the programmed antifuses. No separate testing overhead structure is needed.