The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 22, 1994

Filed:

Sep. 01, 1992
Applicant:
Inventor:

Phillip E Mattison, Gilbert, AZ (US);

Assignee:

VLSI Technology, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ;
U.S. Cl.
CPC ...
327 75 ; 327259 ; 327295 ; 327141 ;
Abstract

A circuit for generating multiple clock edges from a single input clock is disclosed. This circuit has a digital clock input which causes a capacitor to charge and discharge with constant current sources, providing a linear voltage ramp. This linear voltage ramp is monitored by several comparators, each of which have a different reference voltage level, the outputs of which provide the multiple clock edges needed. In this manner, several outputs are generated, each of which has the same fundamental frequency as the input clock signal, but with varying duty cycles and delays from the clock edges of the input clock. In this manner, several clock edges are available for use in synchronous digital systems such as state machines that require precise timing relationships between inputs and clock signals.


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