Master slice gate array integrated circuits with basic cells adaptable

Abstract

The input/output circuit cells of a master-slice gate array device have the same diffusion and gate regions as the basic transistors so that the input/output of the device may be defined at the metallization stage rather than at the time the diffusion regions are formed. Thus a single size master-slice circuit device need to be kept in inventory. The array size is selected in accordance with the customer's specification and the inputs/outputs are defined accordingly using CAD. Thereafter, the die may be scribed into smaller. The transistors for sea-of-gate structures containing a pair of long channel transistors whose drain, gate and source regions lie on a single grid or track of the CAD design tool. By using a long channel transistor in the feedback loop of a memory cell, gating transistors may be eliminated to reduce transistors required for latches. To provide the required drive capability, a number of transistors may be connected to form the input or output buffer, without requiring large transistors with large diffusion regions. A metal silicide resistor and a number of discharge transistors normally in the off condition are connected to the node between an input/output pad and input/output buffer for electrostatic discharge.