The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 15, 1994
Filed:
Oct. 29, 1993
Phillip A Carswell, Mesa, AZ (US);
Steven F Clark, Tempe, AZ (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
A secure cryptographic logic arrangement immediately halts the processing of its internal processors upon detection of a single fault. The cryptographic logic arrangement has an arithmetic logic unit, permuter, and a non-linear combiner. A total self-checking controller monitors each of the arithmetic logic unit, permuter, and non-linear combiner to determine whether a fault has occurred in any one of its internal processors. The total self-checking controller employs a scheme of transmitting a pseudorandom signal to each of the internal processors and compares a phase of the pseudorandom signal received back from each of the internal processors to determine whether a fault exists.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile