The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 15, 1994
Filed:
Oct. 18, 1993
Robert B Manley, Ft. Collins, CO (US);
Hewlett-Packard Company, Palo Alto, CA (US);
Abstract
A CMOS level conversion circuit for converting voltage levels between CMOS levels and shifted ECL levels, where the shifted ECL levels are referenced to the VDD supply voltage of the CMOS circuit. The circuit contains a pFET connected between the VDD supply voltage and the output terminal and an nFET connected between the output terminal and circuit ground. The input signal is connected to the gate input of the nFET. A second pFET is connected in parallel to the nFET between the output terminal and ground. A bias voltage is supplied to the gate inputs of both pFETs, to cause the output terminal to have a shifted ECL logic one voltage when the gate to the nFET is low. The pFETs are fabricated within the integrated circuit to be located very close to each other to compensate for variations in the CMOS integrated circuit manufacturing process.