The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 15, 1994
Filed:
Jul. 23, 1993
Katsuhiro Seta, Tokyo, JP;
Hiroyuki Hara, Fujisawa, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
An input terminal IN is connected to the input of a CMOS inverter, and also to the gate of an N-channel MOS transistor N10. The output of the CMOS inverter is coupled to the base of an NPN transistor Q11 used for pulling up the output terminal OUT. The drain of the transistor N10 is connected to the input of a CMOS inverter. The output of the inverter is connected to the base of an NPN transistor Q12 used for pulling down the output terminal OUT. The emitter of the transistor Q11 and the collector of the transistor Q12 are connected to an output terminal OUT, which is coupled to the gate of a P-channel MOS transistor P12 and the gate of an N-channel MOS transistor N3. The drain of the transistor P12 is connected to the drain of the transistor N10. The drain of the transistor N13 is connected to the source of the transistor N10. The transistors N10, P12, and N13 constitute a circuit for controlling the CMOS inverter.