Semiconductor memory device and process

Abstract

A semiconductor memory device with a storage capacitor is provided which accomplishes a large storage capacity together with a high component density, and facilitates the production. A switching transistor is formed locally in a semiconductor substrate. Formed over the transistor is an upper-level wire disposed over which is a storage capacitor. A storage capacitor contact passes through the upper-level wire. While ensuring a good capacity for the storage capacitor contact, the allowance of focus, too, can advantageously be obtained in simultaneously transferring a pattern of the upper-level wire onto the memory cell region as well as onto the peripheral circuit region. Particularly, by having the storage capacitor contact pass through a bit line, a drain and a source can symmetrically be arranged with a word line, like a memory cell with a bit-line-over-storage-capacitor organization cell. This eliminates an excess portion resulting in increasing the density.