Semiconductor memory with column line control circuits for protection

Abstract

A semiconductor memory device has plural memory cell blocks, each including memory cells storing data therein. A data bus and switching circuits transfer data from the memory cells to the data bus in response to a first logic level signal applied thereto. Column lines each have first and second ends. Each column line is connected to the corresponding switching circuit in each of the memory cell blocks. A column decoder, coupled to the first end of the column lines, provides the first logic level signal to one of the column lines upon the memory cell blocks being accessed. Potential setting circuits are coupled to the second end of the column lines, and preliminarily set the respective column lines to be in a predetermined potential so that each switching circuit is inactive prior to the column decoder providing the first logic level signal. All the memory cells in an array can be prevented from becoming inoperative even if a column line is broken.