The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 1994

Filed:

Aug. 09, 1993
Applicant:
Inventors:

Katsuji Iguchi, Yamato-kooriyama, JP;

Shigeki Hayashida, Kita-katsuragi, JP;

Akio Kawamura, Nara, JP;

Shinichi Sato, Nara, JP;

Tomohiko Tateyama, Nara, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 70 ; 437 46 ; 437 56 ; 437968 ; 148D / ;
Abstract

Element isolation regions are first formed on a silicon substrate. Active regions other than the isolation regions are formed with an oxide film. Then, a first oxidization prevention layer, a semiconductor layer and a second oxidization prevention layer are formed on the substrate in that order. A resist pattern having a hole in a P-channel MOS transistor formation region is formed. The second oxidization prevention layer in the P-channel MOS transistor formation region is removed and an impurity is ion-implanted using the resist pattern as a mask. After removing the resist pattern, the substrate is thermally treated in the presence of an oxidizer substance to transform an exposed portion of the semiconductor layer into an oxidized semiconductor layer and at the same time to diffuse the implanted impurity in the substrate to thereby form an N-well. After removing the remaining second oxidization prevention layer and the semiconductor layer located under the remaining second oxidization prevention layer, an impurity is ion-implanted into the substrate using the oxidized semiconductor layer as a mask, to thereby form a P-well in a N-channel MOS transistor formation region of the substrate. Then the P-channel and N-channel MOS transistors are formed in respective regions.


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