The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 01, 1994
Filed:
Nov. 18, 1992
Richard J Petschauer, Edina, MN (US);
Paul G Johnson, Brooklyn Park, MN (US);
Unisys Corporation, Blue Bell, PA (US);
Abstract
An apparatus and method for improving the testability of six cell CMOS SRAM circuits. The technique involves adding transistors and the ability to effectively disable the precharge circuitry during the test mode. This makes the pull up transistors the only current source for switching the memory cell. An open or weak pull up transistor, which would appear as an intermittent soft failure under operational conditions because of the current sourcing of the precharge circuitry, becomes a hard stuck-at failure under the test conditions. Because the precharge circuitry is disabled for all memory cells, a slower memory clock speed is used for memory cycling during the test mode.