Residue calculation circuit

Abstract

A residue calculation circuit which can achieve increase of the calculation speed and reduction of the scale of an integrated circuit. The residue calculation circuit includes cascade-connected delay circuits, a first stage multiplier and a plurality of multipliers for multiplying an input residue and outputs of the delay circuits by respective coefficients and adding a predetermined correction number to residues of the products, a first adder for adding outputs of the first stage multiplier and a first one of the multipliers and outputting a first stage sum data and a first stage carry signal, a plurality of adders each for adding the output of the first adder or one of the adders at a preceding stage and the output of the corresponding multiplier and outputting a sum data and a carry signal, an accumulation circuit for accumulating reversed values of the carry signals and outputting cumulative data, and a correction circuit for multiplying the cumulative data by the predetermined correction number, subtracting thus obtained cumulative correction data from the sum data outputted from the last stage adder and outputting the resulted data as an output of the residue calculation circuit.