The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 01, 1994
Filed:
Mar. 03, 1993
Craig S Lage, Austin, TX (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
A process for fabricating stacked gate structures (10, 11) and local interconnects (50, 52), in which portions (32, 34) of the thin-film channel layers (20, 22) are exposed by etching away portions of overlying insulating layers (28, 30). A masking layer (40) is formed to overlie the thin-film channel layers (20, 22) and the insulation layers (28, 30), and openings (42, 44) are formed in the insulation layer (40). The openings (42, 44) expose the exposed portions (32, 34) of the thin-film layers (20, 22) and portions (46, 48) of the substrate (12). Interconnects pads (50, 52) are formed to overlie the masking layer (40) and electrically contact the exposed portions of the thinfilm layers (20, 22) and the exposed portions (46,48) of the substrate (12). In regions where the insulation layers (28, 30) have not been removed, an interconnect pad (52) electrically contacts only a portion (48) of the substrate (12 ). In regions where insulation layers (28, 30) are removed, an interconnect pad (50) electrically contacts both the thin-film channel layer (22) and a portion (46) of the substrate (12).