The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 01, 1994

Filed:

Dec. 02, 1993
Applicant:
Inventor:

Katsuhiko Tamura, Hyogo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 43 ; 437 49 ; 437101 ; 437233 ;
Abstract

According to a method of manufacturing a semiconductor device, a monocrystal silicon layer can be formed easily without adversely affecting semiconductor elements. In the method of manufacturing the semiconductor device, a first polysilicon layer is formed on a gate oxide film layer on a silicon substrate, and then a resist is formed on a predetermined region of the first polysilicon layer. Using the resist as a mask, anisotropic etching is effected to expose the surface of the silicon substrate. Thereby, it is not necessary to form the resist directly on the gate oxide film layer, as is done in the prior art, and it is possible to prevent impurity such as sodium or phosphorus in the resist from entering the gate oxide film layer. Consequently, it is possible to prevent a disadvantage such as change of a threshold voltage of a memory cell transistor, which may be caused by the entry of impurity.


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