The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 01, 1994

Filed:

Nov. 12, 1993
Applicant:
Inventors:

Richard A Davis, Plano, TX (US);

Mark Plagens, Richardson, TX (US);

Uppili Sridhar, Garland, TX (US);

Assignee:

Honeywell Inc., Minneapolis, MN (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
C25F / ;
U.S. Cl.
CPC ...
2041293 ;
Abstract

A method is provided for assuring good electrical contact between a power supply and appropriate regions of silicon wafers to assure proper etching during the micromachining of the silicon die locations on the wafer. A plurality of conductors are disposed in the interstices between rows and columns of die locations and each die location that is to be etched is provided with a conductive extension connecting its relevant region with one of the interstice conductors. A preselected number of die locations are dedicated to the purpose of providing conductive pads against which contacts of a power supply can be disposed. The many interconnections between the row interstice conductors and the column interstice conductors assures good electrical distribution across the entire surface of a first side of the wafer.


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