The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 25, 1994

Filed:

May. 04, 1993
Applicant:
Inventors:

Pei-chun P Liu, Austin, TX (US);

Karl Wang, Austin, TX (US);

Assignee:

Motorola, Inc., Schaumburg, IL (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365 49 ; 36518905 ; 36523008 ; 365233 ;
Abstract

A content addressable memory system has a plurality of associated circuit sets (12). Each circuit set has a tag memory element, a latching circuit and a data memory element. Each tag memory element stores a received tag in a first mode of operation and compares a received data tag to a stored data tag in a second mode of operation. In the second mode of operation, the tag memory element couples a first voltage supply terminal to an associated node in response to the comparison. Each latching circuit latches the voltage level present on its associated node during a first phase of a control signal. Each data memory element stores a data word and outputs the data word responsive to the latched voltage level of the associated latching circuit. The latching circuit continues to latch the voltage level and the data memory element continues to output its data word for an entire clock cycle. Each latching circuit couples its associated node to a second voltage supply terminal during a first phase of the control signal.


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