The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 25, 1994
Filed:
Apr. 27, 1990
Toru Shiomi, Hyogo, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
A level converting circuit comprises first and second complementary metal oxide semiconductor (CMOS) inverter circuits, and first and second N-Channel metal oxide semiconductor (NMOS) transistors. The first CMOS inverter circuit and the first transistor are connected in series between a relatively high power supply voltage and a relatively low power supply voltage. The second CMOS inverter circuit and the second NMOS transistor are connected in series between the relatively high power supply voltage and the relatively low power supply voltage. Complementary emitter coupled logic (ECL) level signals are converted into MOS level signals by the first and second CMOS inverter circuits. Current flow from the relatively high power supply voltage to the relatively low power supply voltage is inhibited by the first and second NMOS transistors. The level converting circuit can be used to interface a metal oxide semiconductor (MOS) memory cell array to a bipolar peripheral circuit.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile