Cache prefetch and bypass using stride registers

Abstract

A technique and a mechanism accurately determines the correct prefetch line for loops with strides of 1, N, or a combination of stride values. Stride registers are used to assist in prefetching. Furthermore, stride register values can be used to specify 'cacheability' of data on an object by object basis to prevent 'cache flushing'. The compiler uses a new instruction, 'MOVE GPR TO STRIDE REGISTER', prior to a loop to insert the 'calculated stride value(s)' into the stride register(s) associated with the index register(s) which will be incremented by that stride value. At the end of the loop, a second new instruction, 'CLEAR STRIDE REGISTER SET', is used to place a value of zero in all of the stride registers to inhibit prefetching of data which would most likely not be used. A zero value in the stride registers inhibits prefetching. Non-zero values in the stride registers clearly mark the execution of a loop, which is where prefetching makes the most sense. It also clearly indicates the correct offset from the current address to use in determining the prefetch address. Since the offset is dependent on the particular index register used in specifying the storage address, data for loops with multiple strides can be correctly prefetched. A hardware managed set of stride registers provides a subset of the benefits afforded by the software managed implementation.