The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 18, 1994
Filed:
Sep. 30, 1991
Applicant:
Inventors:
Shigeru Kikuda, Hyogo, JP;
Shigeru Mori, Hyogo, JP;
Yoshikazu Morooka, Hyogo, JP;
Hiroshi Miyamoto, Hyogo, JP;
Makoto Suwa, Hyogo, JP;
Mitsuya Kinoshita, Hyogo, JP;
Assignee:
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
36523003 ; 365 51 ; 365 63 ;
Abstract
A plurality of sub chips are formed on a chip. An input/output buffer region is arranged around the plurality of sub chips. Each sub chip includes a sub chip control circuit region and a plurality of memory cell array blocks. Each memory cell array block includes a memory cell array region, a row decoder and control circuit region, a sense amplifier region and an input/output latch region.
Kikuda, Shigeru. (1994). Semiconductor integrated circuit device including a plurality of cell (U.S. Patent No. 5357478). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5357478
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile