Fault locator architecture and method for memories

Abstract

Architecture for a memory device and a method for employing the architecture for testing of the memory device are provided. In a memory device such as a one-time programmable EPROM, an extra row and an extra column of memory cells are added to the regular array. The extra column is configured so that, during a first test configuration, a sense device connected to the column line of the extra column of cells will detect whether exactly one row line of the correct parity is selected in response to input of a row address. Similarly, the extra row is configured so that the sense amp connected to the column lines of the regular array, can determine whether exactly one column line of the correct parity from the regular array is selected in response to input of a column address. The row decoder and row address lines are tested separately from the testing of the column decoder and column address lines. In this fashion, an EPROM can be tested to obtain single fault coverage for faults in address logic (including address inputs) and certain faults in a memory array without the need to write or program a memory cell. This permits practical testing for the above-mentioned coverage for EPROMs which cannot feasibly be erased such as one-time programmable (OTP) EPROMs.