The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 18, 1994
Filed:
Mar. 26, 1993
Applicant:
Inventor:
Hideyuki Terane, Hyogo, JP;
Assignee:
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364787 ;
Abstract
An adder circuit for adding two 16-bit data to each other includes 16 full adders and three carry look ahead circuits. A plurality of full adders excluding two ones provided on the least significant bit side and two ones provided on the most significant bit side are classified into three groups. Each of the groups includes four full adders. A single carry look ahead circuit is provided for the four full adders forming each group.
Quick Actions:
Terane, Hideyuki. (1994). Adder with carry look ahead circuit (U.S. Patent No. 5357457). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5357457
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile