The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 18, 1994
Filed:
Oct. 04, 1991
Osamu Ichiyoshi, Tokyo, JP;
NEC Corporation, , JP;
Abstract
A first clock signal of fl in frequency is converted into a second clock signal having a frequency of f2=(n/m) f1. The first clock signal is converted by a tank circuit (12) and a converter (13) into an R-bit first phase signal (.theta.1) indicating the phase of the first clock signal. The first phase signal is multiplied by n (mod 2.sup.R) by a multiplier to provide a second phase signal (.theta.3). The second phase signal is supplied to a digital phase-locked loop (PLL) (3) comprising a subtractor (15), a low-pass filter (LPF) (16), a numerically controlled oscillator (NCO) (17) and a multiplier (18). The multiplier in the digital PLL (3) multiplies a third phase signal by m (mod 2.sup.R), indicating the phase of a second clock signal which is the output of the NCO (17), to generate a fourth phase signal. The subtractor (15) generates a signal representing the phase error between the second and fourth phase signals. This phase error signal is filtered by the LPF (16) to control the oscillating phase of the NCO (17). A clock generating circuit generates the second clock signal, on the basis of the third phase signal.