The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 18, 1994
Filed:
Aug. 05, 1993
Fred Sterzer, Princeton, NJ (US);
MMTC, Inc., Princeton, NJ (US);
Abstract
The use of one or more multi-gate (e.g., dual-gate) FETs are employed in an RF or microwave delay line. The carrier drift velocity in each multi-gate FET is controlled in accordance with the variable magnitude of a delay-control voltage applied between its drain and source, thereby controlling the time delay experienced by an RF or microwave signal traveling between spaced first and second gates of a multi-gate FET. The gates of a plurality of multi-gate FETs may be serially-coupled through amplifying circuits to produce a delay chain in which the total delay is the sum of the delays of all the multi-gate FETs in the chain. A single delay-control voltage, which can be continuously variable, may be used to control the total delay provided by all multi-gate FETs in the chain. Alternatively, a separate delay-control voltage, which can be independently continuously variable, may be used for independently controlling the delay provided by each individual multi-gate FET in the chain. RF and microwave analog delay lines are useful in such apparatus as difference-in-time-of-arrival direction finders and transversal filters, by way of example.