Dynamic random access memory cell

Abstract

A memory for a dynamic random access memory includes an isolation trench formed between a pair of cells. Pass gate transistors are formed on either side of the isolation trench, with source/drain regions for contacting to a bit line formed on the opposite side of a gate electrode from the isolation trench. A source/drain region for each transistor is formed between the gate electrode and the isolation trench, and is used for a charge storage capacitor connection. For each transistor, a conductive plug is formed in contact with the capacitor source/drain region and extending vertically above this region and the gate electrode. This conductive plug forms the charge storage node of the capacitor, and is covered by a dielectric layer and a common capacitor reference plate.