The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 18, 1994
Filed:
Jan. 21, 1994
John Lin, Ellicott City, MD (US);
Andras F Cserhati, Columbia, MD (US);
AlliedSignal Inc., Morris Township, Morris County, NJ (US);
Abstract
A method for making all complementary BiCDMOS devices on a SOI substrate (10). Isolated n.sup.- and p.sup.- regions (20,32,34,36,40,42) are formed on the silicon layer (16) and oxidized. LOCOS oxide regions (28) are formed on selected pairs of the n.sup.- and p.sup.- regions on which gates (44) for complementary DMOS device (114,116) and field plates (46) for complementary bipolar devices (118,120) are formed. Gates (48) for complementary MOS devices (122,124) are formed directly on the oxidized silicon layer (24). N-type and p-type dopants are then implanted into the silicon layer (16) forming n body and p body areas (54,56,58,60). Selected n.sup.+ and p.sup.+ areas (66,68) are formed in the n body and p body areas (54,56,58,60) as well as selected areas of n.sup.- and p.sup.- regions (30,32,34,36,40,42). The substrate (10) is then covered with an oxide layer and windows etched therethrough to expose said n.sup.+ and p.sup.+ areas (66,68) and selected areas of the gates (44,48) and field plates (46). Metal electrical contacts (78-112) are deposited through the windows to the n.sup.+ and p.sup.+ areas ( 66,68) and the gates (44,48) and field plates (46).