Data processor for performing simultaneous instruction retirement and

Abstract

A data processing system is provided which has more general purpose physical registers than architectural (logical) registers. The data processing system uses a register inventory system to monitor the allocation state changes of each of the physical registers in a register file. As a sequencer issues instructions, an indexed random access memory (RAM) stores a copy of visible and allocation state bits for each of physical registers. When the sequencer needs to perform a branch repair, the sequencer must back up to the checkpoint where the branch instruction was issued. The visible and allocation bits for each physical register at this checkpoint are read out of the RAM. Using the information read from the RAM, and a predefined back-up deallocation relation, the register inventory system determines which physical registers to deallocate and returns those physical registers to a free pool for future allocation. The register inventory system also allows the sequencer to simultaneously retire any instructions which were completed, and discard any instructions marked by the back-up process.