The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 27, 1994
Filed:
Jul. 06, 1992
William W Cheng, Redondo Beach, CA (US);
Lloyd F Linder, Agoura Hills, CA (US);
Hughes Aircraft Company, Los Angeles, CA (US);
Abstract
A sample and hold circuit uses a Class AB amplifier architecture rather than a diode bridge in a sampling gate. Input and output transistor pairs (Q5, Q6; Q7, Q8) receive an input voltage (Vin) and provide at an output terminal (6) (a) an output voltage that tracks the input signal, and (b) a current from a load dependent current source (Vcc, Vee). The output current used to charge a sample holding capacitor (Ch) is not limited to the input standing current, and operates with a lower quiescent power consumption and better distortion than prior circuits. Complementary bipolar transistors (Q15, Q16, Q17, Q18; Q9, Q10, Q11, Q12) are used in a clock driver circuit and in the sampling gate to compensate for the different operating speeds of the npn and pnp transistors.