Run length limited encoding/decoding system for low power disk drives

Abstract

The run length limited encoding/decoding system of this invention includes a clock swap logic circuit, a read reference clock multiplexer circuit, a write clock skip logic circuit, an encoder start logic circuit, an encoder circuit, a read clock skip logic circuit, a decoder start logic circuit, a decoder circuit, an input data buffer and a three-state output data buffer. The encoder circuit includes a deserializer for receiving serial data from a disk controller and blocking the data into m bit words. Each m bit data word is supplied directly to an encoding combinatorial logic circuit which in turn generates an n bit code word. The n bit code word is loaded in a serializer and serially transmitted out of the serializer. The decoder circuit includes a deserializer/serializer and a decoding combinatorial logic circuit. The deserializer/serializer receives a serial stream of encoded data and converts the data into n bit code words. Each n bit code word is loaded directly into the decoding combinatorial logic circuit which in turn generates an m bit data word. The m bit data word is loaded into the deserializer/serializer so that as the next n bit code word is serially loaded in the deserializer/serializer, the m bit data worded is serially moved out of the deserializer/serializer.