Signal processing arrangements

Abstract

Switched current circuits include current memory cells which store analogue currents by way of the charge on the gate source capacitance of an MOS transistor. A source of inaccuracy in these circuits is switch charge injection into the gate source capacitance. It has been found that the error current produced by a single current memory cell is relatively flat over a current range centered above a peak value of stored current. When two current memory cells are connected in cascade this error may be cancelled. In order to produce equal errors an optimum bias current is generated which depends on parameters variable in integrated circuit manufacturing processes but which are relatively constant within an individual integrated circuit. The two cascaded current memory cells include controllable bias current sources and a control circuit controls the current sources so that the current memory cells operate at the optimum bias current. The control circuit includes two further current memory cells connected in cascade and two different value current sources are provide. The error current due to switch charge injection charges a capacitor (Cx). The voltage across this capacitor controls current sources (T16,T17) and also current sources (T14, T15). The current sources (T14,T15) and capacitor form a control feedback loop that causes the bias current to approximate the optimum value.