The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 1994

Filed:

Apr. 15, 1991
Applicant:
Inventors:

Dhlrubwai N Desai, Santa Clara County, CA (US);

David M Lewis, Santa Cruz County, CA (US);

Don M Robinson, Santa Clara County, CA (US);

Assignee:

Seagate Technology, Inc., Scotts Valley, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395375 ; 364D / ; 364230 ; 3642301 ; 3642303 ; 3642328 ;
Abstract

Connected blocks of micro-instructions are reloaded to a register file in a sequencer, which is used for controlling an interfacing between a host computer, a magnetic disk-drive, and a buffer memory. This provides for efficiently reloading sequencer microinstructions into a relatively small sequencer-memory space and minimizes use of external system resources for reloading microinstructions. This avoids the sequencer having to remain in a wait condition until a system processor completes higher priority tasks and becomes available for reloading instructions to memory cells of the sequencer. The method includes storing a plurality of blocks of microinstructions in a buffer memory device. A first block of microinstructions is stored in a register file. A second block of microinstructions stored within the buffer memory device is called using microinstructions contained within the first block of microinstructions. The second block of microinstructions are loaded into the register file, where the second block of microinstruction contain microinstructions for loading a third block of microinstructions into the register file, and so on. The sequencer interfaces with a buffer memory, which stores a plurality of blocks of microinstructions. A register file stores a first block of microinstructions, where the first block of microinstructions includes microinstructions for selecting a second block of microinstructions from the buffer memory. The first block of microinstruction includes microinstructions for subsequently loading the selected second block of microinstructions into the register file.


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