The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 13, 1994
Filed:
Dec. 14, 1992
Ted Williams, Los Gatos, CA (US);
HaL Computer Systems, Inc., Campbell, CA (US);
Abstract
A multiplier tree sums the partial products of a multiplication operation, employing a regular hierarchical arrangement of bit adders that accept nine initial inputs and a carry input and produce three outputs and a carry output. The regularity of the structure of the bit adder allows it be used to form an array of bit adders to sum twenty-seven input bits and ten carry input bits to produce three output bits and ten carry outputs bits. These bit adders form the basis of the multiplier tree. The multiplier tree using this structure can sum the partial products from a 52 to 54 bit multiply operation in no more adder delays than a Wallace tree, but with a more regular structure. A method for reducing nine input signals to three output signals segregates the input signals into sets of signals and combines them into reduced sets of logically equivalent signals.