The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 13, 1994
Filed:
May. 14, 1993
Yoshito Nishimichi, Osaka, JP;
Matsushita Electric Industrial Co. Ltd., Osaka, JP;
Abstract
A phase locked loop (PLL) is disclosed, which produces a source clock signal which has a frequency twice that of a reference clock signal fed from the outside and is in synchronism with a reference clock signal. A timer counts pulses of a reference clock signal in order to measure time corresponding to the lock-in time of the PLL and delivers a count completion signal when the value of counting reaches a predetermined value. A start controller is in control of a clock buffer so that, after a count completion signal is delivered, the clock buffer starts feeding a source clock signal to a load circuit as an internal clock signal, in synchronism with a reference clock signal. A stop controller is also in control of the clock buffer so that, when a clock stop request signal becomes asserted, the clock buffer stops feeding an internal clock signal, in synchronism with a reference clock signal.