Input clock presence detector for a digital video input

Abstract

A method and apparatus for input data clock presence detection which utilizes an up/down counter clocked by a reference clock, which operates at a nominal frequency rate half of the nominal rate of the input data clock, and an R/S flip-flop causing the up/down counter to count up when set, and to count down when reset. The R/S flip-flop is cleared by the reference clock and set by the input data clock. The counter is selected to count up to its maximum number and remain there when continuously clocked up. Similarly, when continuously clocked down, the counter reaches its minimum number (zero) and remains there. So long as the input data clock is present and has the correct rate, after each reference clock pulse resets the flip-flop and prepares the counter to count down, there is at least one input data clock that sets the flip-flop and prepares the counter to count up. As a result, each reference clock pulse is counted up, and eventually the counter reaches its maximum number indicating presence of the input data clock. In the absence of the input data clock, the R/S flip-flop remains reset, whereupon the reference clock pulses are counted down, and eventually the counter reaches its minimum indicating the absence of the input data clock. A latch is provided for output of the clock presence signal.