The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 30, 1994
Filed:
Jun. 22, 1992
James D Shiffer, II, Fremont, CA (US);
VLSI Technology, Inc., San Jose, CA (US);
Abstract
A transparent power grid is formed using a first metal layer and a second metal layer in a gate array having defined therein well tie-down regions. The first metal layer includes first power supply busses for supplying operating and reference voltages to the transistors, the first power supply busses extending in a row direction and overlapping the well tie-down region. The second metal layer includes second power supply busses for supplying operating and reference voltages to the transistors, the second power supply busses extending in a column direction and overlapping the well tie-down regions and the first power supply busses. Vias are formed where first and second power supply busses each supplying a same one of the operating voltage and the reference voltage overlap, thereby connecting the first and second power supply busses. Contacts are formed where first and second power supply busses each supplying a different one of the operating voltage and the reference voltage overlap, the contacts connecting the first power supply busses to underlying well tie-down regions. In effect, all of the necessary vias and contacts are placed in locations that in the prior art were all occupied by contacts alone.