The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 23, 1994

Filed:

Oct. 16, 1991
Applicant:
Inventors:

Robert E Dean, Boulder, CO (US);

Steven C Cacka, Longmont, CO (US);

Douglas P Schaefer, Lafayette, CO (US);

Hossein F Sevvom, Boulder, CO (US);

Robert A Brumnet, Denver, CO (US);

Assignee:

Storage Technology Corporation, Louisville, CO (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395250 ; 395425 ; 360 722 ; 364D / ; 364239 ; 3642394 ; 3642397 ; 364243 ; 3642434 ; 364253 ; 3642531 ;
Abstract

The address mark triggered read/write head buffer provides a buffer memory for each read/write head in the rotating media data storage system that stores the entire track of data that includes the requested data record. Thus, the address mark triggered read/write head buffer retrieves the requested data record independent of the control module so that a seek request from the processor can be handled as soon as the beginning of the next data record stored on the track is positioned below the associated read/write head. The entire track is thereby staged faster on the average than the time to retrieve the requested data record. The address mark triggered read/write head buffer includes an address mark detection circuit to identify the beginning of the data field in each data record. The address mark is a predetermined data pattern of n bits that is written on the track a predetermined distance in advance of the data field of the data record. The address mark detection circuit compares the n data bits most recently read from the track with this predetermined data pattern of n bits as stored in memory. Once a match is detected, the buffer is enabled to store the next data record written on the track and all subsequent data records on the track.


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